1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Conventionally, there has been used a semiconductor device including an isolation region (STI: Shallow Trench Isolation) structure formed by burying an insulating film in a trench provided in a semiconductor substrate. In this semiconductor device, a region divided off by the STI structure serves as an active region. In addition, there has been conventionally used a method for forming trenches for burying gates in a semiconductor substrate, in addition to STI trenches, and burying gate electrodes in the trenches, in order to optimize the gate length of a transistor.
JP2011-159739A discloses a semiconductor device in which an active region isolated by STI is formed, and a gate electrode is formed as buried wiring. Paragraph 0014 of JP2011-159739A discloses that burial failures, such as voids, are liable to occur inside an insulating film buried in linear trench portion 401 in the vicinity of wide connection trench 402. As measures against these failures, JP2011-159739A discloses forming the planar shape of an isolation trench into a shape small in width variation in the method described in the patent document (paragraph 0020). In addition, JP2011-159739A discloses, in FIG. 30 thereof, a peripheral region which exists so as to surround a memory cell region and protrudes toward the memory cell region side at the boundary thereof with the peripheral region.
FIG. 26 is a schematic plan view illustrating the layout of isolation regions, element-forming regions (hereinafter, described as active regions in some cases), and buried wiring of DRAM 200 according to the related art, where intermediate parts are excluded from the illustration. DRAM 200 includes memory cell region 60, and peripheral region 61 in which driving transistors (not illustrated) are disposed outside memory cell region 60. Peripheral region 61 is composed of isolation region (STI) 59, Y peripheral region 62 extending in a Y direction, and X peripheral region 63A extending in an X direction. Element isolation trench 4 which defines the planar shape of STI 9 includes a plurality of linear trench portions 65 extending in a direction intersecting with the Y direction, and crank-shaped trench portions 66 sandwiched between a plurality of active regions 1A located on the Y-direction edge side of memory cell region 60 and X peripheral region 63A. Here, one boundary portion 67 of X peripheral region 63A in DRAM 200 has a crank shape, whereas the other boundary portion 68 has a linear shape. Consequently, the Y-direction width of X peripheral region 63A has a minimum value of Y5 and a maximum value of Y6.
In this DRAM 200, silicon in active regions composing X peripheral region 63A is simultaneously dry-etched along with STI 9 when forming trenches for buried wiring 5 composed of gate electrodes. At this time, the side etching of each active region progresses further with a decrease in the width of each active region. Thus, side etching reaches as far as the central portion of the active region. As a result, etching from the upper surface of the active region is accelerated. Accordingly, a narrow active region becomes smaller in height than an active region which is so wide that side etching does not reach the central part of the active region.
In such DRAM 200 of the related art as illustrated in FIG. 26, the Y-direction width of X peripheral region 63A varies from the minimum value Y5 to the maximum value Y6, thus causing a variation in the amount of side etching at the time of forming trenches for gate electrode 5 on the X peripheral region 63A. As a result, the height of active regions composing X peripheral region 63A (the height of the upper surfaces of the active regions composing the bottoms of trenches for gate electrode 5) also varies. The present inventors have found that if gate electrode 5 is buried in the trenches under this condition, the film thickness of gate electrode 5 also varies, thus causing a variation in the wiring resistance of gate electrode 5.